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Codasip | Codasip Adopts Imperas for RISC-V Processor Verification

Oxford, United Kingdom & Munich, Germany – 22 November 2021 – Imperas Software Ltd., the chief in verification options for RISC-V, and Codasip, the chief in customizable RISC-V processor IP, at present introduced that Codasip has adopted Imperas reference designs and the Imperas DV resolution for Codasip IP. Codasip has invested closely into processor verification to ship the trade’s highest high quality RISC-V processors.

Codasip has included Imperas golden reference fashions in its DV testbenches to make sure an environment friendly verification circulation that accommodates a variety of versatile options and choices whereas scaling throughout your complete roadmap of future cores to allow rigorous affirmation of purposeful high quality.

Codasip Verification

Codasip Verification

RISC-V is a modular structure that gives many various permutations of base directions, normal elective extensions and customized directions – that raises considerations about implementations and the chance of fragmentation. Codasip’s inner testing already makes use of an inner instruction-accurate mannequin, a number of sources of direct and random testing (inner and externally offered), and a number of other completely different applied sciences to test and guarantee processor compliance. Imperas configurable reference fashions are already totally examined and allow all of the configuration choices wanted to help this complete view.

The Codasip engineering staff based mostly in Sophia-Antipolis, France, reviewed the challenges of the evolving RISC-V specs, the complete Codasip processor IP portfolio, extensions and configurable options, plus future roadmap plans. Imperas options have been discovered to be best to help the operational workload and scale necessities. The Codasip engineering staff set-up the infrastructure and check frameworks across the Imperas RISC-V Reference Models to effectively check all configurations with the flexibility to adapt for brand new roadmap options.

“Imperas are the pioneers in simulation technology and processor verification for RISC-V,” mentioned Philippe Luc, Verification Director Codasip. “While processor verification is not a new problem, there are many RISC-V suppliers, with customization and various levels of verification or conformance: customers are legitimately concerned about both quality and fragmentation. Codasip is very proud of our rigorous approach to verification– using Imperas as an important part of our quality process furthers extend our differentiation. The Imperas independence, reputation and technical strength provides our customers with further reassurance in our ‘best in class’ RISC-V processors.”

Simon Davidmann, CEO at Imperas Software Ltd, added, “Codasip provides the RISC-V market with a range of processor solutions that enable optimized performance for a wide range of applications. Design verification of this processor IP is fundamental to Codasip continuing to deliver the highest-quality processors as it moves to the next generation of its IP. Each additional optional feature roughly doubles the verification workload. The Imperas approach supports Codasip’s development by applying Continuous Integration/Continuous Development to a sophisticated processor DV environment by using simulation and offers an efficiency advantage without compromising optional features. Imperas and Codasip share a common vision that improved quality is essential to the success of RISC-V.”

Availability
The Imperas RISC-V Reference Models for Codasip can be found now to guide prospects and companions for software program growth and as a basis for digital platforms.

RISC-V Summit
The RISC-V Summit and DAC are co-located for 2021, December 6-Eight in San Francisco, CA. Imperas is a Diamond Sponsor for the RISC-V Summit 2021, extra particulars on all of the keynotes, talks and to request a demos can be found at this hyperlink: https://www.imperas.com/articles/imperas-risc-v-summit-december-6-8-2021.

Codasip is a Platinum Sponsor for RISC-V Summit 2021, details about its attendance, our keynote and different shows, and to rearrange a gathering with our staff, go to right here: https://codasip.com/news-docs/events/risc-v-summit-2021/.

About Codasip
Codasip delivers modern RISC-V processor IP and high-level processor design instruments, offering IC designers with all the benefits of the RISC-V open ISA, together with the distinctive capacity to customise the processor IP. As a founding member of RISC-V International and a long-term provider of LLVM and GNU-based processor options, Codasip is dedicated to open requirements for embedded and software processors. Formed in 2014 and headquartered in Munich, Germany, Codasip at the moment has R&D facilities in Europe and gross sales representatives worldwide. For extra details about our services and products, go to www.codasip.com. For extra details about RISC-V, go to www.riscv.org.

About Imperas
Imperas is the main supplier of RISC-V processor fashions, {hardware} design verification options, and digital prototypes for software program simulation. Imperas, together with Open Virtual Platforms (OVP), promotes open supply mannequin availability for a spectrum of processors, IP distributors, CPU architectures, system IP and reference platform fashions of processors and programs starting from easy single core naked metallic platforms to full heterogeneous multi-core programs booting SMP Linux. All fashions can be found from Imperas at www.imperas.com and the Open Virtual Platforms (OVP) web site.

For extra details about Imperas, please see www.imperas.com. Follow Imperas on LinkedIn, twitter @ImperasSoftware and YouTube.

Media Contacts
David Marsden
PR & Marketing
david.marsden@codasip.com
+44 7968 407739

Roddy Urquhart
Codasip Group
Senior Marketing Director
rurquhart@codasip.com
+44 753 158 7023

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